Advanced Low-Power Digital Circuit Techniques by Muhammad S. Elrabaa

By Muhammad S. Elrabaa

Advanced Low-Power electronic Circuit Techniques provides numerous novel excessive functionality electronic circuit designs that emphasize low-power and low-voltage operation. those circuits symbolize quite a lot of circuits which are utilized in state of the art VLSI platforms and consequently function solid examples for low-power layout. every one bankruptcy includes a short creation that serves as a brief heritage and offers the inducement in the back of the layout. every one bankruptcy additionally ends with a precis that in short explains the contributions contained therein. This makes the ebook very readable. The reader can skim during the chapters in a short time to get a suppose for the layout difficulties provided within the booklet and the suggestions proposed by means of the authors. Examples of circuits utilized in platforms the place low-power is necessary from reliability and portability issues of view (such as general-purpose and DSP processors) are offered in Chapters 2, three and four. Chapters five and seven supply examples of circuits utilized in platforms the place reliability and extra procedure integration are the most riding forces in the back of decreasing the facility intake. bankruptcy 6 supplies an instance of a normal objective high-performance low-power circuit layout.
Advanced Low-Power electronic Circuit Techniques is a true designer's booklet. It investigates substitute circuit kinds, in addition to architectural possible choices, and provides quantitative effects for comparability in lifelike applied sciences. a number of of the circuits offered were fabricated in order that simulations could be checked. The circuits lined are crucial development blocks for plenty of designs, so the textual content should be of direct use to designers. MOS designs are coated, in addition to BiCMOS, and there are numerous novel circuits.

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For example, the modified Radix-2 algorithm is based on partitioning the multiplier into overlapping groups of 3-bits, and each group is decoded to generate the correct partial product . 5) In this equation, the terms in brackets have values in the set{ -2 , -1, 0, +1, +2}. 0, +1, +2. 1. 1 Partial product selection . Y Zi+l Y Zi YZ i - l 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Recod ed digit 0 +1 +1 +2 -2 -1 -1 0 Op era tion on X ox X +1 x X +1 x X +2 x X -2 x X - 1x X -1 x X ox X The bits of the mult iplier (Y ) a re par titioned int o groups of overlapping 3bits, each group permits the genera tio n of a certain partial product .

2 Low-Po wer High-Performan ce A dders 21 60 CPL-CLA ~ DPL-CLA ~ TG -CLA IlJl TG-MAN m TG-CS ~ Cony . CSA-CPL LJ CSA-TG 0 50 40 - 30 • (/) c:: >. 8 Effect of V D D scaling o n the adders ' d elay. LO ...... -CLA CSA-CPL 0 CSA-TG 0 1500 -.. 9 MHz. 7 LAYOUT STRATEGY The CSA-CPL circuit was laid out for fabrication in order to perform an experimental evaluation of the circuit. 8Jlm CMOS (in BiCMOS) process . In constructing the circuit layout, consideration was given to minimizing the critical path routing capacitance.

1) '1 == ali' "%j ~ Yl3 Yll Y ........ g .... 2 Simulation Strategy Simulation of a complex circuit such as a 16xl6-bit multiplier is slow and difficult to use in the initial stages of the design process. 9), is a regular array of identical cells. It is therefore possible to replace most of the cells by their equivalent input capacitance and to study the performance of only a few of the basic building blocks under appropriate loading conditions. After the initial design is complete, a full simulation is then run to verify operation and obtain more accurate results.

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