Cellular Neural Networks and Analog VLSI by J. M. Cruz, L. O. Chua (auth.), Leon O. Chua, Glenn Gulak,
By J. M. Cruz, L. O. Chua (auth.), Leon O. Chua, Glenn Gulak, Edmund Pierzchala, Angel Rodríguez-Vázquez (eds.)
Cellular Neural Networks and Analog VLSI brings jointly in a single position vital contributions and up to date study ends up in this fast paced sector.
Cellular Neural Networks and Analog VLSI serves as a very good reference, delivering perception into one of the most demanding learn matters within the field.
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Additional resources for Cellular Neural Networks and Analog VLSI
Es Received October I, 1996; Accepted November 26, 1996 Abstract. In this paper, three alternative VLSI analog implementations of CNNs are described, which have been devised to perform image processing and vision tasks: a programmable low-power CNN with embedded photosensors, a compact fixed-template CNN based on unipolar current-mode signals, and basic CMOS circuits to implement an extended CNN model using spikes. The first two VLSI approaches are intended for focal-plane image processing applications.
6. The energy consumption for a digital implementation (-) of a pole as a function of the required dynamic range; the minimal energy consumption of analog implementations due to the impact of mismatch (-o-) or noise (-x-). where the proportionality constant is fixed by the circuit architecture; Cox is the transistor gate capacitance per unit area and is a technology constant inversely proportional to the gate-oxide thickness. IPower is fixed by the used VLSI technology. Moreover mismatch imposes a boundary on the minimal power consumption P of an analog VLSI signal processing system to achieve a given accuracy or dynamic range DR and a given speed or signal frequency f Thermal noise also imposes a limit of the power consumption P of analog circuits for a given operation frequency f and dynamic range DR, expressed as: 8 kT f DR2 , where k is the Boltzmann constant and T the absolute temperature.
Ortega. " IEEE Transactions on Circuits and Systems Part 140 (3), pp. 215-219. March 1993. 7. S. Espejo, A. Rodriguez-Vazquez, R. Dominguez-Castro, J. L. Huertas. and E. Sanchez-Sinencio. " IEEE Journal of Solid· State Circuits 29 (8), August 1994. 8. F. Sargeni and V. " in Proceedings of the CNNA-94, Rome, 1994. pp. 67-72. 9. A. Paasio, A. Dawidziuk, K. Halonen. and V. Porra, "Current mode cellular neural network with digitally adjustable template coefficients," in Proceedings Microneuro '94, IEEE Compo Soc.