Exploring Memory Hierarchy Design with Emerging Memory by Guangyu Sun

By Guangyu Sun

This booklet equips readers with instruments for machine structure of excessive functionality, low strength, and excessive reliability reminiscence hierarchy in desktops in accordance with rising reminiscence applied sciences, akin to STTRAM, PCM, FBDRAM, and so on. The innovations defined supply merits of excessive density, near-zero static strength, and immunity to smooth error, that have the potential for overcoming the “memory wall.” The authors speak about reminiscence layout from numerous views: rising reminiscence applied sciences are hired within the reminiscence hierarchy with novel structure amendment; hybrid reminiscence constitution is brought to leverage merits from a number of reminiscence applied sciences; an analytical version named “Moguls” is brought to discover quantitatively the optimization layout of a reminiscence hierarchy; ultimately, the vulnerability of the CMPs to radiation-based gentle error is better by means of changing various degrees of on-chip reminiscence with STT-RAMs.

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Consequently, we can generate similar global frequent values in FV tables with different profiling periods. The FVratios, however, decrease a little when the profiling period is too long. The reason is that it takes longer time to fill the FV table with a longer profiling period. Based on these results, we use 213 of write operations as the profiling period. It requires 13 counting bits in each entry of WAC table. 4 Evaluation of Endurance The improvement of lifetime is evaluated by iteratively running these applications till a failure happens in one PRAM memory cell.

3), we design an SRAM-STTRAM hybrid L2 cache with 31 ways of STTRAM and 1 way of STTRAM (31M1S). After having these hybrid cache lines, the second step is how to distribute STTRAM cache lines and SRAM ones into separate cache banks. Considering the SRAM part is the minority in the proposed 31M1S cache, one partitioning alternative is to distribute these SRAM cache lines into different banks so that there are at least several SRAM cache lines close to each processing core. However, this method requires each cache bank as a heterogeneous memory array with SRAM and STTRAM cells and increases the complexity of the cache design.

3 Frequent-Value Based PCM Memory 39 benefits from increasing FV-ratio, and total write intensity to PRAM memory may be increased. In addition, the hardware overhead is increased as the FV length is reduced. As shown in Fig. 24, the access to each data block is in parallel so that the impact on performance is minimized. Consequently, the number of duplicated peripheral circuitry equals to the number of data block in a PRAM memory line, which is decided by FV length. FV number also has an impact on performance of the memory architecture.

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