Fabrication of SiGe HBT BiCMOS Technology by John D. Cressler

By John D. Cressler

SiGe HBT BiCMOS know-how is the most obvious groundbreaker of the Si heterostructures software area. thus far almost each significant participant within the communications electronics industry both has SiGe up and working in-house or is utilizing an individual else’s SiGe fab as foundry for his or her designers. Key to this good fortune lies in profitable integration of the SiGe HBT and Si CMOS, without lack of functionality from both machine. jam-packed with contributions from major specialists, Fabrication of SiGe HBT BiCMOS applied sciences brings jointly an entire dialogue of those issues right into a unmarried source. Drawn from the great and well-reviewed Silicon Heterostructure instruction manual, this quantity examines the layout, fabrication, and alertness of silicon heterostructure transistors. a singular element of this booklet the inclusion of diverse picture perspectives of the commercial state of the art for SiGe HBT BiCMOS expertise. it's been rigorously designed to supply an invaluable foundation of comparability for the present prestige and destiny process the worldwide undefined. as well as the copious technical fabric and the various references contained in every one bankruptcy, the ebook comprises easy-to-reference appendices at the homes of Si and Ge, the generalized Moll-Ross relatives, necessary charge-control kin, and pattern SiGe HBT compact version parameters.

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R. ) have significant deltas from the base CMOS latch-up and ESD specifications. A more conservative flow is to select the starting wafer resistivity to be compatible with the base CMOS process or just slightly higher with a typical number around 10 ohm-cm. The formation of the subcollector involves another tradeoff. For the lowest subcollector resistance, a low resistivity buried subcollector is desirable.

8. A Gruhle. Prospects for 200 GHz on silicon with SiGe heterojunction bipolar transistors. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 19–25. 9. DL Harame, DC Ahlgren, DD Coolbaugh, JS Dunn, G Freeman, JD Gillis, RA Groves, GN Henderson, RA Johnson, AJ Joseph, S Subbanna, AM Victor, KM Watson, CS Webster, and PJ Zampardi. Current status and future trends of SiGe BiCMOS technology. IEEE Transactions on Electron Devices 48:2575–2594, 2001. 10. R Singh, DL Harame, and MM Oprysko.

Have significant deltas from the base CMOS latch-up and ESD specifications. A more conservative flow is to select the starting wafer resistivity to be compatible with the base CMOS process or just slightly higher with a typical number around 10 ohm-cm. The formation of the subcollector involves another tradeoff. For the lowest subcollector resistance, a low resistivity buried subcollector is desirable.

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