Multi-Level Simulation for VLSI Design by Dwight D. Hill, David R. Coelho (auth.)

By Dwight D. Hill, David R. Coelho (auth.)

AND historical past 1. 1 CAD, Specification and Simulation laptop Aided layout (CAD) is this present day a normal expression bearing on the research of the way during which pcs can be utilized to expedite the layout method. this may comprise the layout of actual structures, architectural environments, production approaches, and lots of different parts. This ebook concentrates on one zone of CAD: the layout of computers. inside this zone, it focusses on simply features of computing device layout, the specification and the simulation of electronic platforms. VLSI layout calls for help in lots of different CAD parts, induding automated format. IC fabrication research, attempt new release, and others. the matter of specification is exclusive, even if, in that it i!> usually the 1st one encountered in huge chip designs, and one who is not going ever to be thoroughly computerized. this is often actual simply because till a design's targets are laid out in a machine-readable shape, there isn't any approach for different CAD instruments to ensure that the objective procedure meets them. And except the necessities could be simulated, it really is not likely that designers could have self belief in them, because requirements are very likely faulty themselves. (In this context the time period objective procedure refers back to the and/or software program that might eventually be fabricated. ) nonetheless, because the performance of a VLSI chip is eventually decided by means of its structure geometry, one may query the necessity for CAD instruments that paintings with parts except layout.

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Suppose that it were decided to use two-way, one-bit multiplexers of component type bitm and connect them as shown in Figure 2-3. Each component accepts the net type boolnet which represents a single electrical connection. - - I I I I I _______ JI '--- I sensor2 (sensor) Figure 2·3. Low-Level Design of Multiplexer To simulate the behavior of this system it is necessary to define another component type in ADLIB; this time it is bitm. But once this is done, the design can be validated in two ways: the overall system can be simulated to see if it behaves the same with the multiplexer subsystem in place of sense_mult in Figure 2-1.

5] :=regc [21 .. 20 ]//regd [21 .. 19]; rega[1 .. 1] :"regd[13 .. 13]; Figure 3·7. Assignment of Register Variables Figure 3-7 shows several examples of register value assignments. Each variable shown above corresponds to the declarations of Figure 3-6. In the first statement, the entire contents of regc are copied to regd. In the second statement, three bits of regb are given the values associated with three bits of rega. In the third statement, two strings of bits associated with registers regc and regd are concatenated and assigned to a portion of rega.

The purpose of a module file is to allow related collections of models to be stored in a single file. In addition, models can be split between several module files, allowing greater flexibility in compilation and development of models. Through the USE statement, any module file can include all subroutines associated with a package file. Since packages are precompiled, this approach is efficient, and allows modular development of subroutines. 11 Global Identifiers The models shown in Figure 3-11 and 3-12 are not much different from the contour model of a Pascal program.

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