System-on-Chip Methodologies & Design Languages by Robert H. Klenke, James H. Aylor, Paul Menchini, Ron Waxman,

By Robert H. Klenke, James H. Aylor, Paul Menchini, Ron Waxman, William Anderson (auth.), Peter J. Ashenden, Jean P. Mermet, Ralf Seepold (eds.)

System-on-Chip Methodologies & layout Languages brings jointly a range of the simplest papers from 3 foreign digital layout language meetings in 2000. The meetings are the Description Language convention and Exhibition (HDLCon), held within the Silicon Valley sector of united states; the discussion board on layout Languages (FDL), held in Europe; and the Asia Pacific Chip layout Language (APChDL) convention. The papers conceal a variety of issues, together with layout tools, specification and modeling languages, device concerns, formal verification, simulation and synthesis. the consequences provided in those papers may also help researchers and working towards engineers retain abreast of advancements during this quickly evolving field.

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3] A Jerraya and R. Ernst. Multi-language System Design. In Proceedings ofthe Conference on Design, Automation and Test in Europe, pages 696-699, Munich, Germany, 1999. [4] E. Lee and A Sangiovanni-Vincentelli. Comparing Models of Computation. In Proceedings of the International Conference on Computer Aided Design, San Jose, 1996. [5] P. Schwarz and C. Clauss. KOSIM - An Experimental Simulator for Heterogeneous Systems. In Proceedings ofthe Workshop on Mixed-Signal and Mixed-Level Simulation, Munich, Germany, 1999.

3 (a». This format is used by the CADDY-II synthesis system representing a language independent input description. 3 (b». This has to be done only if new frame components have been inserted in the library. Finally, CADDY-II can execute the usual high-level synthesis process. 1). Not only user-defined operators, but also several standard operators can be used. The standard operators are defined in the IEEE std_logic_ arithm package, and therefore, need not to be specified in the object-oriented component library.

For software processes control is passed to their run method until this method exits. It is the responsibility of the user to ensure that this method terminates. Otherwise the simulation gets caught in an infinite cycle. As previously stated, sensitivity sets of software processes are calculated statically at instantiation time. However, sensitivity sets of VHDL processes must be calculated dynamically at each execution of a wait statement. Finally, the exi t method is called for each process once at the 42 end of simulation.

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