Transient-Induced Latchup in CMOS Integrated Circuits by Ming-Dou Ker

By Ming-Dou Ker

The booklet all semiconductor equipment engineers needs to learn to realize a realistic think for latchup-induced failure to provide lower-cost and higher-density chips.Transient-Induced Latchup in CMOS built-in Circuits  equips the working towards engineer with the entire instruments had to deal with this universal challenge whereas turning into more adept at IC format. Ker and Hsu introduce the phenomenon and easy actual mechanism of latchup, explaining the severe matters that experience resurfaced for CMOS applied sciences. as soon as readers can achieve an realizing of the normal practices for TLU, Ker and Hsu speak about the actual mechanism of TLU below a system-level ESD try, whereas introducing an effective component-level TLU size setup. The authors then current experimental methodologies to extract secure and area-efficient compact format principles for latchup prevention, together with structure ideas for I/O cells, inner circuits, and among I/O and inner circuits. The ebook concludes with an appendix giving a pragmatic instance of extracting structure ideas and directions for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process.Presents actual instances and recommendations that ensue in advertisement CMOS IC chipsEquips engineers with the talents to preserve chip structure zone and reduce time-to-marketWritten via specialists with real-world adventure in circuit layout and failure analysisDistilled from quite a few classes taught via the authors in IC layout homes worldwideThe simply booklet to introduce TLU less than system-level ESD and EFT testsThis booklet is vital for practising engineers eager about IC layout, IC layout administration, process and alertness layout, reliability, and failure research. Undergraduate and postgraduate scholars, focusing on CMOS circuit layout and format, will locate this booklet to be a worthwhile advent to real-world difficulties and a key reference in the course of the process their careers.

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Afterwards, IDD will greatly increase while VDD returns to above 0V, and therefore TLU does occur. As a result, both the VDD and IDD waveforms are slightly oscillatory under a low-impedance (high-current) latchup state. Finally, VDD will eventually be pulled down to about the DC latchup holding voltage (~1V) with a huge IDD (~80 mA) after this transition. 18: Measured VDD and IDD transient waveforms from the TLU test with a negative VCharge of -5V. 5V. (Reprinted with permission from IEEE). 18, the experimental results are consistent with the device simulation results in the time domain.

194–198. [18] Mahanpour, M. and Morgan, I. (1995) The correlation between latch-up phenomenon and other failure mechanisms. Proceedings of the Electrical Overstress/Electrostatic Discharge Symposium, 17th Conference, pp. 289–294. [19] Voldman, S. (September/October 2003) Latch-up – it’s back, Threshold Newsletter, ESD Association, Rome, NY, USA. , Esmark, K. et al. (2003) Transient latch-up: experimental analysis and device simulation. Proceedings of the Electrical Overstress/Electrostatic Discharge Symposium, 25th Conference, pp.

461–472, Sep. 2006. IEEE, Piscataway, NJ. Chapter 3 - Component-Level Measurement for TLU under System-Level ESD Considerations Transient-Induced Latchup in CMOS Integrated Circuits by Ming-Dou Ker and Sheng-Fu Hsu John Wiley & Sons © 2009 Citation Recommend? 2 Component-Level TLU Measurement Setup The SCR structure is used as the test structure for TLU measurements because the occurrence of latchup results from the parasitic SCR in CMOS ICs. 5a and b, respectively. The geometrical parameters such as D, S, and W represent the distances between thewell-edge and well (substrate) contact, anode and cathode, and the adjacent contacts, respectively.

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