VHDL’92 by Jean-Michel Bergé, Alain Fonkoua, Serge Maginot, Jacques
By Jean-Michel Bergé, Alain Fonkoua, Serge Maginot, Jacques Rouillard (auth.)
An open means of restandardization, carried out by way of the IEEE, has resulted in the definitions of the hot VHDL common. The alterations make VHDL more secure, extra moveable, and extra robust. VHDL additionally turns into higher and extra entire. The canonical simulator of VHDL is enriched by means of new mechanisms, the predefined surroundings is extra entire, and the syntax is extra common and versatile. Discrepancies and recognized insects of VHDL'87 were mounted. in spite of the fact that, the recent VHDL'92 is appropriate with VHDL'87, with a few minor exceptions.
This e-book provides the recent VHDL'92 for the VHDL dressmaker. New gains ar defined and labeled. Examples are supplied, every one new function is given a motive and its influence on layout method, and function is analysed. the place acceptable, pitfalls and traps are explained.
The VHDL fashion designer will fast have the ability to locate the function had to review the advantages it brings, to switch earlier VHDL'87 code to make it extra effective, extra moveable, and extra flexible.
VHDL'92 is the basic replace for all VHDL designers and executives enthusiastic about digital design.
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Extra resources for VHDL’92
Wrong Use of Direct Instantiation? It may seem very appealing to use direct instantiation all the time to avoid the "verbosity" of the component declaration and component configuration specification. But this would not be very wise because of the reusability overhead. This point is illustrated by the example of a simple adder. Assume that the following units are available in the library NMOS: entity NMOS_AND is port( INPUT1,INPUT2 : BIT; OUTPUT: out BIT); end entity NMOS_AND; entity NMOS_OR is port( INPUT1,INPUT2 : BIT; OUTPUT: out BIT); end entity NMOS_OR; entity NMOS_XOR is port( INPUT1,INPUT2 : BIT; OUTPUT: out BIT); end entity NMOS_XOR; with the corresponding architectures.
The only solution is to create cut/paste operations to replace the references to NMOS library components by references to the new library component. This may represent a huge overhead and a nonneglectable risk of error in the case of very complex devices. Obviously, this kind of approach does not fit with good methodology. The natural VHDL solution to increase the reusability of such structural models is to gather all binding information in configuration declarations. For this, general-purpose packages can be written containing component declarations independent of any particular technology.
A common practice in VHDL is to bind components to design units with configuration specifications written into the architecture (where the components are instantiated). , in configuration declarations. Such a two-step binding specification is possible in VHDL'92, which introduces an incremental binding mechanism. Another related issue concerning the binding specification is the default binding mechanism. The definition of default binding in VHDL'87 contains some ambiguities and omissions that have been clarified in VHDL'92.